instruction execution

Activity is a unit of instruction execution , and is the building block of a process .

活动（activity）是指令执行的一个单元，它是一个流程的基本组成部分。

The article essentially describes such points as instruction execution and memory management in constructing a virtual running embedded system .

文中着重介绍了构建嵌入式虚拟运行平台中的指令执行、存储器管理等核心技术问题。

In other words , software interrupts always occur at the beginning of an instruction execution cycle .

换句话说，软件中断常常在指令运行周期的开始。

In the instruction execution pipeline stage , scalable pipeline technology was adopted to realize the video processing instruction .

为有效实现扩展指令，处理器执行级采用了可扩展流水级技术。

If supervision engineer issued a directive , contractor should change by supervision engineer change instruction execution .

若监理工程师发出了变更指令，承包人就应按监理工程师的变更指令执行。

It is shown that the MCU core 's maximum clock frequency and instruction execution speed are three times higher than traditional MCS-51 core .

验证结果表明：所设计的微处理器核在最高时钟频率和最高指令执行速度方面均优于传统典型微控制器MCS-8051内核的3倍以上。

Bochs was developed purely in the C + + language for interpreted x86 instruction execution and platform emulation .

对于解译的x86指令执行和平台仿真，Bochs完全是用C++语言开发的。

Characteristics of the microprocessor are fast speed and nimble instructions . The way of raising speed is to adopt pipelining in instruction execution .

它的运算速度提高的途径是指令的执行采用流水线方式，指令缓冲部件IB采用两个体交替接收指令和执行指令的办法来减少取指令的等待时间。

The platform introduces two memory system structure , addressing mode simulation guarantees that not only the operand is correctly obtained , but also the instruction execution time is correctly calculated .

采用了两种存储器体系结构，寻址方式的模拟不仅保证了正确地确定操作数，而且能够正确统计指令执行时间。

The Digital Signal Processing which is regarded as CPU on board has some advantages , such as fast instruction execution , high bus bandwidth , and high speed real-time data processing .

数据采集卡部分使用使用DSP来作采集卡CPU具有指令执行速度快、总线带宽高、可以完成数据的高速实时处理等优点。

But in reality , the upper software drives the underlying hardware , for example different instruction execution and data access affect the underlying hardware circuit directly and result in different power generation .

但在实际情况中，底层硬件受上层软件驱动，例如不同指令执行和数据存取等软件指令直接影响底层硬件的电路活动，导致不同功耗产生。

A new type of microprocessor is introduced in this paper . The microcontroller core is compatible with 8051.It uses an efficient 8051 core that results in an improved instruction execution speed and low power consumption .

介绍TI公司推出的一款用于数据采集系统的MSC1201型微处理器，该电路具有与8051型微处理器完全兼容的内核，执行速度更快，功耗更低。

Compile the assembler into machine code so that generate PLE file in order to implement the execution mechanism of PLC virtual machine . In this way , the instruction execution speed of PLC is greatly increased and we can save much memory .

用汇编编译器编译转变成功的汇编程序产生机器码，从而构造出可执行文件&PLE文件，实现PLC虚拟机的机器码执行机制，这样大大提高了PLC指令的执行速度，同时大大节约了内存空间。

This paper has discussed the relationship between the machine cycle and instruction execution time for superscalar RISC architecture , issuing multiple instructions in one machine cycle . Several new design features of superscalar RISC architecture with single execution unit and multiple function units have been analysed .

本文讨论超标量RISC结构中单周期发多条指令中周期和执行指令时间的相对关系，并分析了新型超标量RISC结构的实现方案，其中包括具有单个执行部件和多个执行部件的结构。

Traditional programming model like C , C + + and Fortran are poorly suited to multi-core architectures because of the assumed single instruction stream execution model and centralized memory structure .

C、C++和Fortran等基于单指令流和统一存储结构的传统编程模型已经无法适应多核处理器结构。

This article probes into a kind of encryption method for files , which is different from the usual way . It also studies the encryption method for instruction inverse execution , which means how to use inverse instruction stream to realize the file encryption .

研究一种打破常规的文件加密方法，指令的逆运动加密方法，即如何采用逆指令流来实现对计算机文件的加密。

A technique whereby the receiver fetches the next instruction before completing execution of the previous instruction , in order to increase processing speed .

在前一条指令全部执行完之前就开始取下一条指令，以提高处理速度的一种技术。

As the core of SOC , CPU ′ s performance is mostly determined by instruction ′ s execution efficiency . Pipeline increases the instruction ′ s execution pace and improves the CPU ′ s performance .

作为SOC的核心，CPU的性能主要取决于指令的执行效率，而采用流水线方式大大增加了指令的执行速度，提高了CPU的性能。

The model of instruction level parallel program execution

指令级并行程序执行模型

A4-stage instruction pipeline for instruction execution makes at-speed test possible .

四级指令流水线的引入使全速测试成为可能。

Static instruction scheduling decides the execution order of instructions and improves the instruction-level parallelism by reducing stall caused by dependences .

静态指令调度决定指令执行顺序，屏蔽指令间由于依赖关系而产生的延迟，从而提高了指令的并行度。

In the traditional Cache , the Cache hit ratio is insured only by the address locality of memory reference instruction stream during program execution , it restricts the improvement of Cache hit ratio .

在传统的Cache中，仅仅依靠程序执行时访存指令流地址的局域性来保证较高的Cache命中率，使得Cache命中率的提高受到限制。

Composite electronic System is the hinge of the Pico-satellite , which undertakes the work of data processing , data storage , data transmission , Instruction code transmission and Instruction execution .

综合电子系统是皮卫星的数据和指令枢纽，承担皮卫星数据处理、数据存储、数据传输及指令收发、响应等重要任务，是皮卫星的核心组成部分。

Propose the run time dispatched instruction decoder and issue logic based on instruction execution cycle .

提出基于指令类型动态分配的译码器设计方案和基于指令执行周期的动态逻辑发射方案。